A wide variety of electronic systems use memory modules. Personal computers (PC's) use memory modules as the main memory on the PC motherboard. Memory modules are built to meet specifications set by industry standards, thus ensuring a wide potential market. High-volume production and competition have driven module costs down dramatically, benefiting buyers of a wide variety of electronic systems.
Memory modules are made in many different sizes and capacities, such as older 30-pin and 72-pin single-inline memory modules (SIMMs) and newer 168-pin, 184-pin, and 240-pin dual inline memory modules (DIMMs). The “pins” were originally pins extending from the module's edge, but now most modules are leadless, having metal contact pads or leads. The modules are small in size, being about 3-5 inches long and about an inch to an inch and a half in height.
The modules contain a small printed-circuit board substrate, typically a multi-layer board with alternating laminated layers of fiberglass insulation and foil or metal interconnect layers. Surface mounted components such as DRAM chips and capacitors are soldered onto one or both surfaces of the substrate.
FIG. 1 shows an illustration of a fully-buffered memory module. Memory module 10 contains a substrate such as a multi-layer printed-circuit board (PCB) with surface-mounted DRAM chips 22 mounted to the front surface or side of the substrate, as shown in FIG. 1, while more DRAM chips 22 are mounted to the back side or surface of the substrate (not shown). Memory module 10 could be a fully-buffered dual-inline memory module (FB-DIMM) that is fully buffered by an Advanced Memory Buffer (AMB) chip (not shown) on memory module 10. The AMB chip uses differential signaling and packets to transfer data at high rates.
Memory modules without an AMB chip are still being made. Such unbuffered memory modules carry address, data, and control signals across metal contact pads 12 from the motherboard directly to DRAM chips 22. Some memory modules use simple buffers that buffer or latch some of these signals but do not use the more complex serial-packet interface of a FB-DIMM.
Metal contact pads 12 are positioned along the bottom edge of the module on both front and back surfaces. Metal contact pads 12 mate with pads on a module socket to electrically connect the module to a PC's motherboard. Holes 16 are present on some kinds of modules to ensure that the module is correctly positioned in the socket. Notches 14 also ensure correct insertion of the module. Capacitors or other discrete components are surface-mounted on the substrate to filter noise from the DRAM chips 22.
Some memory modules include a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module substrate. SPD-EEPROM 130 stores configuration information for the memory module, such as speed, depth, and arrangement of the memory on the memory module.
PC-Based Memory-Module Tester—FIG. 2
FIG. 2 shows a memory-module tester that is constructed from a personal computer PC motherboard. See for example U.S. Pat. Nos. 6,357,022, 6,351,827, and 6,742,144.
While memory modules could be manually inserted into a memory module test socket on the tester, a memory-module handler that automates insertion and removal of memory modules is desirable. Handler 60 is mounted close to the backside of the PC motherboard using handler adaptor board 50. Handler 60 is not drawn to scale since it is several times larger than a PC motherboard.
Handler 60 is mounted by reverse attachment to the solder-side of the PC motherboard rather than to the component-side of the PC motherboard. The memory module socket on the component side of the PC motherboard is removed, and handler adapter board 50 is plugged from the backside into the holes on the PC motherboard for the memory module socket. Handler adapter board 50 is a small epoxy-glass circuit board designed to interface a handler to a PC motherboard.
Contactor pins 66 within handler 60 clamp down onto leadless pads on the edge of module-under-test MUT 70 when arm 76 pushes MUT 70 into place for testing. Contactor pins 66 include enough pins for all power, ground, and I/O leads on MUT 70.
Contactor pins 66 are electrically connected to connectors on the backside of handler 60. These connectors are edge-type connectors that normally connect with high-speed testers. Typically two connectors are provided. These male-type connectors fit into female-type connectors 54 mounted on handler adaptor board 50. Handler adaptor board 50 contains metal wiring traces formed therein that route signals from connectors 54 to adaptor pins 52 that protrude out the other side of handler adaptor board 50.
Adaptor pins 52 can be directly soldered to PC motherboard substrate 80 using the holes exposed when the memory-module socket was removed, or adaptor pins 52 can be plugged into female pins 55 that are soldered onto solder-side 84 of the PC motherboard. Female pins 55 have extensions that fit into the through-holes exposed by removal of the SIMM socket, but also have cup-like receptacles for receiving adaptor pins 52. Using female pins 55 allows handler adaptor board 50 to be easily removed from substrate 80.
Once MUT 70 has been tested by a test program running on the PC motherboard, MUT 70 is sorted and drops down into either good bin 72 or bad bin 74. Sorting is in response to a pass/fail signal from the test program running on the PC motherboard.
Substrate 80 of the PC motherboard is a conventional multi-layer epoxy-fiberglass circuit board. Components 92, 94 are mounted on component-side 82 of substrate 80. Memory modules 87 fit into memory module sockets 88 that have metal pins that fit through holes in substrate 80. These pins are soldered to solder-side 84 of substrate 80 to rigidly attach sockets to the PC motherboard. Expansion cards 96 are plugged into expansion sockets that are also mounted onto component-side 82 of substrate 80. Cables 98 that are plugged into expansion cards 96 connect peripherals such as disk drives, video display monitors, and multimedia devices to the PC.
Since the memory module tester is constructed from an inexpensive PC motherboard, the cost of the tester is several orders of magnitude smaller than the cost of a million-dollar automated-test-equipment (ATE) machine. Thus test costs are significantly reduced by using a PC-motherboard-based tester. Many different test patterns may be applied to the memory module under test, and the voltages and temperature may be varied to perform corner testing. Hot or cold air may be blown onto the memory module under test by a nozzle (not shown), while the voltage applied to the memory module under test may be adjusted by handler adaptor board 50 or by the PC motherboard.
FIG. 3 shows electrical wiring on a memory module. Memory module 10 has connector 32 that mates with a memory module socket on motherboard 28. Memory module 10 is an unbuffered memory module with DRAM address signals A13:0, bank addresses BA1:0, and other control signals such as RAS, CAS, WE, and any clock or clock-enable signals passing directly through connector 32.
Most of these signals from connector 32 pass directly to DRAM chips 40 over traces 34 on the substrate of memory module 10. Both row and column addresses are input through multiplexed address lines. The row address is applied to the address lines, then RAS is driven low and DRAM chips 40 latch in the row address and begin accessing all columns in the row. Then the column address is applied to the same address lines, and CAS is driven low. DRAM chips 40 use the column address to select one of the columns of data in the selected row.
A few bank address inputs such as BA1:0 may also be supported. Bank addresses are not multiplexed and are usually applied with the row address. Bank addresses might select one of several memory arrays within the DRAM chip.
Some memory modules include a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module substrate. SPD-EEPROM 130 stores configuration information for the memory module, such as speed, depth, and arrangement of the memory on the memory module.
During initialization, the host processor on motherboard 28 reads the configuration from SPD-EEPROM 130. The configuration information about memory module 10 is sent over serial data line SPD_D synchronized to SPD clock SPD_CLK. Address inputs to SPD EEPROM 130 are carried from motherboard 28 on address lines SPD_A[2:0], which may be hard wired on motherboard 28. The wiring configuration of SPD_A[2:0] on motherboard 28 determines the device address (memory-module slot number) of memory module 10. Data sent over serial data line SPD_D is a series of frames consisting of device address, device type, register location, and register data.
DRAM chips may have a very large capacity, such as 512 Mbits, or half a giga-bit. The large number of memory cells, small size of individual memory cells, and overall large area of the DRAM die cause manufacturing defects to be somewhat common. DRAM chips are tested on a wafer before being separated and packaged, but this wafer-sort test may not catch all defects.
Thus some packaged DRAM chips are going to contain defects. Further testing of packaged DRAM chips may be performed cost-effectively at higher speeds, allowing defective DRAM chips to be identified and discarded. Manufacturers may build DRAM chips into memory modules, then perform testing on a low-cost memory module tester constructed from a PC motherboard.
FIG. 4 shows a memory map of a PC motherboard with a test socket for testing memory modules at a low address. The memory space of the microprocessor on a PC motherboard has the basic input-output system (BIOS) mapped to the highest addresses in the memory space. The BIOS code may be read from a read-only memory (ROM) and copied to a memory module inserted into DRAM module slot 566 during booting. Later in the boot process, an image of the operating system (OS) is loaded into the lowest addresses in the memory space, in DRAM module slot 562.
A special test program used by the memory module manufacturer can be loaded into the memory module in DRAM module slot 562 after booting. DRAM module slot 562 can have installed in it a memory module under test that has been inserted into test socket 560 on a test adaptor board, rather than a memory module installed on the PC motherboard. However, when the memory module under test is faulty, defect 56 may occur in the test program or in the OS image, causing the PC motherboard to crash. Ideally, defect 56 is not in the memory portion assigned to DRAM module slot 562 that contains the OS image, but in another portion tested by the test program in DRAM module slot 562. Then the test program may crash, or it may report the failure.
However, when defect 56 in the memory modules device under test occurs in the portion of DRAM module slot 562 that contains the OS image, the PC motherboard is likely to crash during booting or just after booting. This is less desirable, since the test program cannot report the location of the faulty memory. The test system can still detect the error by the motherboard crashing, and can discard the memory module under test in test socket 560.
FIG. 5 shows a memory map of a PC motherboard with a test socket for testing memory modules at a high address. Rather than connect test socket 560 to low addresses of DRAM module slot 562, test socket 560 is connected to the terminals for DRAM module slot 566 on the motherboard. The memory module under test then contains the highest memory addresses in the PC.
Since the BIOS is copied to DRAM module slot 566, the BIOS is copied to the memory module under test. Should a faulty DRAM location occur where the BIOS is loaded, the PC motherboard may crash during booting before the test program is executed. This is undesirable since the exact location of defect 56 within the memory module under test cannot be readily determined. However, the test system can still detect the error by the motherboard crashing, and can discard the memory module under test in test socket 560.
It is often desirable to find the exact location of the defect within a memory module. For example, if the defect location is known, then the DRAM memory chip containing this defect can be removed from the memory module substrate, and a new DRAM chip can be soldered onto the memory module in a rework process. This rework process can save the defective memory module.
Diagnosis of faults may be desired during development, such as to determine the cause of the fault. Statistics may be generated of fault locations to determine if a certain part of the memory module design is weak. A re-design of the memory module may then improve manufacturing yields.
What is desired is a PC motherboard tester that can determine the location of a defect in a faulty memory module. A motherboard tester that does not crash when a faulty memory module is being tested is desirable. A motherboard tester that can isolate a faulty memory location using a test program is desirable.